1. Field of the Invention
This invention generally relates to clock and data recovery (CDR) communications and, more particularly, to a system and method for detecting a clock false frequency lock condition in a CDR device.
2. Description of the Related Art
To efficiently transmit digital information distances longer than the internal bus of a computer, the information can be serialized to encode the bit stream and clock together. The resulting signal is less affected by noise and the transfer function of the transmission medium, as the data and clock experience the same delay. At the receiving end, the timing information is extracted, and the bit stream regenerated. Many classes of digital data streams, especially high-speed serial data streams, are sent as a “raw” stream of data without an accompanying clock. Conventionally, the approximate frequency or baud rate of the raw data is known, the receiver generates a clock from a frequency reference, and then phase-aligns to the reference clock to transitions in the raw data stream using a phase-locked loop (PLL). This process is commonly known as CDR.
In order for the clock to be recovered from raw data, the data stream must transition frequently enough to correct for any drift in the PLL's oscillator. The limit as to how long a clock recovery unit can operate without a transition is known as the maximum consecutive identical digits (CID) specification. To ensure frequent transitions, some sort of encoding is conventionally used; 8B/10B encoding is very common, while Manchester encoding serves the same purpose in old revisions of 802.3 local area networks.
The received information is inevitably affected by some deterioration, as the recovered signals are not exactly synchronous with the transmit clock. Thus, timing information that is essentially carried by the level transitions of the received signal is affected by the noise and by the intersymbol interference. Delay is acquired due to physical transit time and latencies in the receive circuitry.
Conventionally, the clock recovery unit associated with the CDR relies on the pre-programmed ratio between a reference clock (refclk) and the frequency of the input data stream. The recovered clock frequency and the refclk frequency are compared using two frequency counters. If the amount of time it takes the two frequency counter to overflow is about the same, it is concluded that no false locking has occurred. This method of clock recovery requires that the CDR be set up with a particular oscillator(s) and the PLL programmed for particular division ratios. Once the CDR is set up, it is difficult to modify, so as to accept new of different frequencies.
Further, the CDR is prone to false locking. False locking occurs when data stream input to the CDR is not at the same frequency as the recovered clock. This problem is especially prevalent if the CDR is expected to simultaneously recover multiple information streams at different data rates, or if a single received data stream operates at more than one rate.
It would be advantageous if the clock frequency of a raw data stream could be recovered without a refclk frequency. It would be advantageous if the clock frequency of a raw data stream could be recovered without a priori knowledge of the approximate frequency of the data.